2-bit Binary Comparator Logic Circuit Example

2-bit Binary Comparator

A 2-bit magnitude comparator compares A[1:0] and B[1:0] and asserts EQ (equal), GT (A > B), or LT (A < B). XNOR gates detect bit-wise equality; AND/NOT gates encode greater-than and less-than conditions from the MSB.

סוג תרשים שערים לוגייםתקן IEEE Std 91/91a-1991מנוע schematex-logicעודכן 27.5.2026

הבקשה

“Draw a two-bit binary comparator with A1, A0, B1 and B0 inputs and EQ, GT and LT outputs using XNOR, AND, NOT and OR gates.”

ואז נסוAdd a cascade input for larger words.Change it to a three-bit comparator.

מה מופיע בתרשים הזה

פענחו את ההחלטות שמאחוריו.

01XNOR gates produce 1 when bits are equal

used by both EQ and the conditional GT/LT logic.

02MSB checked first

if A1>B1, GT=1 regardless of lower bits.

All intermediate signals named explicitly so gate count and critical path are traceable.

Cascade two 2-bit comparators with equality carry-in/carry-out for a 4-bit comparator.

עיון בכל תבניות ה־תרשים שערים לוגיים ←