シナリオ
Design an 8-bit serial-in parallel-out shift register with clock and clear for data buffering.
この図に含まれるもの
図の背後にある意思決定を読み解く。
01
Use eight D flip-flops in series.
02
Connect Q of each stage to D of the next.
03
Provide a common clock and clear signal.
When a serial data stream needs to be converted to parallel, e.g., in serial communication receivers.