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digital electronics · sequential logic

SR Latch

An SR latch stores one bit using set and reset inputs. The set input requests one output state, while reset requests the opposite state; after either input is released, the latch retains its last valid state. Q and Q-bar provide complementary outputs. Unlike a flip-flop, a basic SR latch is not edge-triggered, so its inputs must be controlled carefully. This diagram is useful for introducing bistable logic, interlocks and simple state retention. Avoid the prohibited input combination for the chosen NOR or NAND implementation.

Typ SchaltplanStandard IEEE Std 315 / ANSI Y32.2Engine schematex-circuitAktualisiert 24.9.2026
SR Latch
Drawing preview
Die Anfrage

“Draw a 5 V NOR SR latch with set and reset inputs and Q and Q-bar outputs, each with a 10 kΩ load to ground.”

Dann probieren SieAdd an enable input.Change it to a NAND SR latch.
Was diese Zeichnung zeigt

Die dahinterstehenden Entscheidungen verstehen.

01Set input

Set requests Q high.

02Reset input

Reset requests Q low.

03Complementary outputs

Q and Q-bar expose the stored state.

Use this to explain basic latch behavior before clocked flip-flops.

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FAQ

Häufige Fragen

What does an SR latch store?

It stores one binary state until a set or reset input changes it.

Is an SR latch edge-triggered?

A basic SR latch is level-sensitive, not edge-triggered.

Why are Q and Q-bar both shown?

They show the stored state and its complement.