Das Szenario
A D-type flip-flop is clocked; data changes too close to a clock edge cause setup or hold timing violations, leading to metastable Q output.
Was diese Zeichnung zeigt
Die dahinterstehenden Entscheidungen verstehen.
01
Illustrate normal operation first, then a setup violation (D changes just before clock edge), and a hold violation (D changes immediately after clock edge), showing corresponding Q metastability.
When teaching or reviewing digital circuit timing constraints, especially in sequential logic design.