Le scénario
A PLC student must implement a two-phase signalized intersection controller as their first timer sequencing lab.
Ce que contient ce dessin
Comprenez les décisions qui le sous-tendent.
01
Phase bits (PHASE_NS, PHASE_EW) set/reset by a master sequence rung — decouples phase logic from output logic.
02
Green and yellow share the same phase bit; yellow enabled only when green timer DN fires.
03
XIO on timer.DN ensures each light turns off exactly when its timer expires, preventing simultaneous green outputs.
Add a pedestrian-call XIC to extend the green phase; add a left-turn arrow rung for a 4-phase intersection.