D Flip-Flop Divide-by-Two Circuit

A D flip-flop can become a divide-by-two circuit when its complemented output is connected back to D. Each active clock edge then captures the opposite of the present Q state, causing Q to toggle. The result is an output with half the input clock frequency and a near-even duty cycle when the source clock is regular. This pattern is a building block for binary counters and clock-divider chains. The diagram shows the feedback explicitly so the relationship between Q-bar, D and the divided Q output is easy to trace.

種類 回路図規格 IEEE Std 315 / ANSI Y32.2エンジン schematex-circuit更新日 2026/9/24

依頼内容

“Draw a 5 V 74HC74 D flip-flop wired as a divide-by-two circuit by feeding Q-bar back to D, with a clock input and Q output.”

次はこちらAdd an active-low clear input.Cascade a second divide-by-two stage.

この図に含まれるもの

図の背後にある意思決定を読み解く。

01Q-bar feedback

Feeding the inverse output to D makes Q toggle on each clock edge.

02Clock input

The input clock is the source frequency.

03Q output

Q is the divided frequency output.

Use this when a digital design needs one half-rate clock or toggle stage.

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よくある質問

Why does Q divide the clock by two?

Q toggles once for every clock edge, so a full output cycle takes two input clock cycles.

What connection makes the divider work?

The complemented output Q-bar is fed back to the D input.

Can dividers be cascaded?

Yes, cascading toggle stages produces further binary divisions.