D Flip-Flop Divide-by-Two Circuit
A D flip-flop can become a divide-by-two circuit when its complemented output is connected back to D. Each active clock edge then captures the opposite of the present Q state, causing Q to toggle. The result is an output with half the input clock frequency and a near-even duty cycle when the source clock is regular. This pattern is a building block for binary counters and clock-divider chains. The diagram shows the feedback explicitly so the relationship between Q-bar, D and the divided Q output is easy to trace.
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Scenario
A clock divider made from one storage element.
Key decisions
- Q-bar feedback: Feeding the inverse output to D makes Q toggle on each clock edge.
- Clock input: The input clock is the source frequency.
- Q output: Q is the divided frequency output.
When to reuse this
Use this when a digital design needs one half-rate clock or toggle stage.
Frequently asked questions
Why does Q divide the clock by two?
What connection makes the divider work?
Can dividers be cascaded?
More digital electronics examples
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