JK Flip-Flop
A JK flip-flop is a clocked storage element with two control inputs. At the active clock edge, J and K can command set, reset or hold behavior; when both are high, the output toggles. This avoids the invalid input state associated with a simple SR latch. The diagram labels J, K, clock, Q and Q-bar explicitly, making it useful for timing discussions and counter design. A JK flip-flop can be configured as a toggle stage by tying J and K high, or adapted for other logic functions with appropriate input connections.
Open it in the AI editor with a prompt pre-filled — keep what works, change what doesn't.
Scenario
A versatile clocked state element.
Key decisions
- J and K inputs: The pair controls set, reset, hold and toggle behavior.
- Clock input: State changes occur on the active clock edge.
- Outputs: Q and Q-bar provide complementary state signals.
When to reuse this
Use this for counters or demonstrations of JK flip-flop behavior.
Frequently asked questions
What happens when J and K are both high?
How is JK different from SR?
What is JK toggle mode used for?
Tweak it with chat, export PNG/SVG, or fork it for your own use case.