4-to-1 Multiplexer Logic Circuit Example

4:1 Multiplexer

A 4:1 multiplexer routes one of four data inputs (D0–D3) to the output Y based on a 2-bit select code (S1, S0). Each input is gated by an AND with its decoded select combination; two OR stages merge the four paths.

種類 論理ゲート図規格 IEEE Std 91/91a-1991エンジン schematex-logic更新日 2026/5/27

シナリオ

A digital logic student building a data-routing unit in an ALU needs a gate-level 4:1 MUX schematic.

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Select decoder uses NOT/AND to generate four mutually exclusive select signals a0-a3.

Two-level OR tree avoids a 4-input OR gate, keeping fan-in at 2.

Each data path is AND-gated independently for straightforward truth table verification.

Cascade two 4:1 MUXes plus one 2:1 MUX for an 8:1 MUX; use as a function generator for any 4-variable Boolean function.

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