A solicitação
“Draw timing for a four-bit register with an eight-cycle clock, asynchronous reset asserted for two cycles, four D values, and Q held reset before showing captured values.”
Depois, tenteAdd a clock-enable signal.Change reset to active low.
O que há neste desenho
Entenda as decisões por trás dele.
01
Asynchronous reset overrides clock
02
Output forced low within same time step as reset assertion
03
Data captured on next clock edge after reset de-assertion
Use for any sequential digital circuit with an asynchronous reset to verify timing behavior.