Das Szenario
Design a transistor-level circuit for a 3-input CMOS NOR gate.
Was diese Zeichnung zeigt
Die dahinterstehenden Entscheidungen verstehen.
01
Three PMOS transistors in series pull output high when all inputs are low
02
Three NMOS transistors in parallel pull output low when any input is high
Use for illustrating CMOS combinational logic, teaching digital IC design, or analyzing CMOS gate structure.