ChatDiagram
ELECTRONICS

CMOS 3-Input XOR Gate

This CMOS 3-input XOR gate circuit implements the parity function Y = A XOR B XOR C with two cascaded sections of a 74HC86 quad XOR IC. The first gate combines A and B and produces intermediate net X. The second gate combines X with C to produce Y. A 5 V VDD supply and ground reference are shown, along with three labeled 5 V logic input sources and a 10 kΩ output load.

UPDATED 2026-09-24
TYPECircuit
USE-CASECmos Logic Gate Circuits
EXAMPLECMOS 3-Input XOR Gate
Make this diagram your own.

Open it in the AI editor with a prompt pre-filled — keep what works, change what doesn't.

CASE ANALYSIS

Scenario

A designer needs a simple CMOS schematic for the odd-parity function Y = A XOR B XOR C. Two sections of a 74HC86 provide the two-input stages, with explicit supply, inputs, and output load so the netlist is electrically closed.

Key decisions

  • Cascaded XOR stages: U1 produces intermediate net X from A and B, and U2 combines X with C.
  • CMOS supply: VDD is supplied at 5 V with node 0 as the return reference.
  • Defined inputs: Separate A, B, and C sources make every logic input a connected net.
  • Output loading: A 10 kΩ load from Y to ground gives the output a defined connected load.

When to reuse this

Use this circuit for a 5 V CMOS three-input parity function built from a 74HC86. Verify input drive levels, fan-out, decoupling, and the specific package pinout before hardware use.

FAQ

Frequently asked questions

What logic function does this circuit implement?01
Y is high when an odd number of A, B, and C are high; it is a three-input XOR or odd-parity function.
Why are two 74HC86 gates used?02
A 74HC86 contains two-input XOR gates, so one gate forms A XOR B and the next combines that result with C.
What is net X?03
X is the intermediate output of the first XOR stage and the first input to the second stage.
Does the 10 kΩ resistor set the logic level?04
No. It is an output load to ground; the 74HC86 output still actively drives Y high or low.
← See more cmos logic gate circuits examples
Open this example in the editor →

Tweak it with chat, export PNG/SVG, or fork it for your own use case.