Timing Diagram · Timing

I2C read burst timing — Timing Diagram

WaveDrom-compatible timing diagram for an I2C register read with address, repeated start, data bytes, ACK, and NACK phases.

Type Timing / waveform diagramStandard WaveDrom-compatible signal descriptionEngine schematex-timingUpdated 5/26/2026

Signal Timing

I2C read burst timing

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The scenario

I2C reads are visually clearer as timing diagrams than as prose. The repeated start and ACK/NACK phases are where firmware and hardware teams most often talk past each other.

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