D flip-flop propagation delay timing

A D flip-flop timing diagram compares the clock, reset, input data and registered Q output. Data changes are shown against a common clock, while Q changes after the applicable capture edge to make the propagation delay visible. The reset interval establishes a known starting state before normal operation. This drawing is useful in a classroom, design review or interface specification because it separates the data waveform from the state held by the register. For implementation work, add clock-enable behavior, asynchronous controls, setup and hold windows, and technology-specific delay values where needed. A timing diagram communicates the intended relationship between signals; it does not replace static timing analysis.