D Flip-Flop with Clear and Preset

A D flip-flop with clear and preset provides ordinary clocked storage plus direct state control. The D input is sampled at the clock edge, while the active-low clear and preset inputs can force Q low or high independently of the clock. These asynchronous controls are commonly used to establish a known state during reset, although they must be used according to the device timing rules. The diagram keeps the data, clock and control pins explicit so a reader can distinguish normal operation from initialization. It is useful for teaching, digital design notes and small control circuits.

유형 회로도표준 IEEE Std 315 / ANSI Y32.2엔진 schematex-circuit업데이트됨 2026. 9. 24.

요청 내용

“Draw a 5 V 74HC74 D flip-flop with D, clock, active-low clear and preset inputs, plus Q and Q-bar outputs with 10 kΩ loads to ground.”

그렇다면Tie the preset input high.Add a reset push button.

이 도면에 담긴 내용

그 이면의 의사결정을 읽어 보세요.

01Clear input

Clear forces the stored state low.

02Preset input

Preset forces the stored state high.

03Separate controls

Both asynchronous controls are drawn independently.

Use this for logic that must initialize or override state without waiting for a clock.

모든 회로도 템플릿 보기 →

자주 묻는 질문

What is asynchronous clear?

It forces the output to a defined state without waiting for a clock edge.

Can preset and clear be asserted together?

That condition is device-specific and is generally avoided unless the datasheet defines it.

Why are the control pins active low?

Many logic families use active-low asynchronous controls, indicated by the bar in the signal name.