D Flip-Flop with Clear and Preset
A D flip-flop with clear and preset provides ordinary clocked storage plus direct state control. The D input is sampled at the clock edge, while the active-low clear and preset inputs can force Q low or high independently of the clock. These asynchronous controls are commonly used to establish a known state during reset, although they must be used according to the device timing rules. The diagram keeps the data, clock and control pins explicit so a reader can distinguish normal operation from initialization. It is useful for teaching, digital design notes and small control circuits.
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Scenario
A register bit that needs asynchronous initialization.
Key decisions
- Clear input: Clear forces the stored state low.
- Preset input: Preset forces the stored state high.
- Separate controls: Both asynchronous controls are drawn independently.
When to reuse this
Use this for logic that must initialize or override state without waiting for a clock.
Frequently asked questions
What is asynchronous clear?
Can preset and clear be asserted together?
Why are the control pins active low?
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