シナリオ
A hardware team is designing a RISC-V in-order processor with on-chip caches for an IoT SoC. The block diagram helps partition the design, assign teams, and understand data flows between pipeline stages and memory.
この図に含まれるもの
図の背後にある意思決定を読み解く。
01
In-order 5-stage pipeline (Fetch, Decode, Execute, Writeback)
02
Split L1 instruction and data caches for parallel access
03
Unified L2 cache to balance area and hit rate
04
External DRAM interface through memory controller
When conveying the high-level microarchitecture of a RISC-V core with cache subsystem to system architects, verification engineers, or students.