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Flip-flop diagram maker.

Create a flip-flop diagram for SR, D, JK or T logic. Describe the input pins, active clock edge, optional reset or preset controls, and the Q and Q-bar outputs your sequential circuit needs.

Circuit SchematicEnter to send

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See it work

Flip-flop diagram examples.

Same tool, four requests. Every drawing below is a real render.

What you type
Draw a 5 V NOR SR latch with set and reset inputs and Q and Q-bar outputs, each with a 10 kΩ load to ground.
Then tryAdd an enable input.Change it to a NAND SR latch.
Circuit schematic: SR latch
Circuit schematic · IEEE Std 315 / ANSI Y32.2 · schematex-circuit

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The drawing

What a flip-flop is.

A flip-flop is a bistable digital circuit that stores one bit. In a clocked design, it changes state only at a defined clock edge, then holds its output until the next state change.

Different types use different inputs: SR uses set and reset, D captures data, JK can toggle, and T toggles when enabled. Q and Q-bar show the stored state and its complement.

Standard
IEEE Std 315 / ANSI Y32.2
Engine
schematex-circuit
Editable
Double-click text, drag nodes
Export
SVG · PNG · PDF
Circuit schematic: What a flip-flop is
Who uses it

Who uses flip-flop diagrams.

Circuit schematic: Digital electronics studentsDigital electronics students

Comparing latch, D, JK and T behavior while learning sequential logic.

Circuit schematic: Counter designersCounter designers

Toggle stages for binary counters and clock-division chains.

Circuit schematic: Control-system designersControl-system designers

Clocked state elements sketched with clear input and output relationships.

How it works

How to make a flip-flop diagram in three steps.

01

Describe it

One paragraph is enough to start.

“Draw a 5 V NOR SR latch with set and reset inputs and Q and Q-bar outputs, each with a 10 kΩ load to ground.”
02

See the drawing

Drawn by the right engine.

Circuit schematic: SR latch
03

Say what changes

Every edit keeps a version.

Add an enable input.
V2 · DRAWN FROM V1, NOTHING RETYPED
FAQ

Common questions

What types of flip-flops can I diagram?

You can describe SR, D, JK and T flip-flops with their inputs, clock and complementary outputs.

What is the difference between a latch and a flip-flop?

A latch is level-sensitive, while a flip-flop is normally edge-triggered by a clock.

What are preset and clear inputs?

They are control inputs that can force a known output state, often independently of the clock.

Why are Q and Q-bar shown together?

They provide both the stored value and its logical complement for downstream circuitry.

Related tools

Other drawings for the same work.

Draw your flip-flop diagram now.

Free account, no card. Describe the flip-flop type, inputs and clock.

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